How does vhdl works

These additional features enable VHDL to precisely represent operations that are customary in hardware. Another feature of VHDL is it has file output and input capabilities that you can utilize as a general-purpose language for text processing. Although, we typically see them in use by a simulation testbench for data verification or stimulus.

Specific VHDL compilers build executable binaries, which afford the option to use VHDL to write a testbench for functionality verification designs utilizing files on the host computer to compare expected results, user interaction, and define stimuli. Note: Ada is a statically typed, structured, object-oriented, and imperative high-level programming language; it is an extension that derives from Pascal and other programming languages.

Its name, Ada, refers to Ada Lovelace Ada King; — , the Countess of Lovelace, who we credit as being the first computer programmer. The critical advantage of VHDL, with regard to system design utilization, is that it permits the behavior of the essential system to be verified and modeled in advance of the synthesis tools translation of the design into actual gates and wires hardware.

VHDL projects are also portable, which means that you can generate a project for one element base and then port it on another element base, such as VLSI, with a variety of technologies.

Using VHDL affords the user concurrent system descriptions. VHDL is a dataflow language, which means it can simultaneously consider every statement for execution. Each of these languages runs a sequence of statements, both sequentially and a single instruction at a time.

One of the more advantageous benefits of VHDL is that its projects are multipurpose; you create the project once and you can utilize the calculation block in various other projects. This means you have the ability to make changes, such as to parameters, element base, memory size, block composition, interconnection structure, and capacity.

It employs a textual format to describe electronic systems and circuits. In the area of electronic design , we apply Verilog for verification via simulation for testability analysis, fault grading, logic synthesis, and timing analysis.

Verilog is also more compact since the language is more of an actual hardware modeling language. As a result, you typically write fewer lines of code, and it elicits a comparison to the C language. However, Verilog has a superior grasp on hardware modeling as well as a lower level of programming constructs. Verilog is not as wordy as VHDL, which accounts for its compact nature. It received its first publication in , with a subsequent revision in SystemVerilog, which is the revision of Verilog, is the latest publication of the standard.

Note: The PLI is a collective of software routines that allows a bidirectional interface between other languages such as C and Verilog. Strongly typed. Weakly typed. Easier to understand. Less code to write. More natural in use. More of a hardware modeling language. Non-C-like syntax. Similarities to the C language. Variables must be described by data type. A lower level of programming constructs. Widely used for FPGAs and military.

A better grasp on hardware modeling. More difficult to learn. Simpler to learn. Like the majority of choices one must make in the field of electronics, it typically centers around the functional advantages. This system affords designers the ability to write much more structured code, and this is particularly useful if declaring record types.

In summary, there are varying opinions as to which language is superior, however, it really just comes down to personal preference. Verilog affords faster, more accurate designs and verification. Thankfully, with our PCB Design and Analysis overview page , you will be sure to have your designers and production teams working together towards utilizing the appropriate HDL for all of your company's design and manufacturing needs.

Whether you are utilizing a single-sided board or a multi-layer design, you will need the right set of PCB layout and design software. The type defines the set of values that the object can have and the set of operations that are allowed on it. The notion of type is key to VHDL since it is a strongly typed language that requires each object to be of a certain type. In general one is not allowed to assign a value of one type to an object of another data type e.

There are four classes of data types: scalar, composite, access and file types. The scalar types represent a single value and are ordered so that relational operations can be performed on them. The scalar type includes integer, real, and enumerated types of Boolean and Character. Examples of these will be given further on. Data Types defined in the Standard Package.

VHDL has several predefined types in the standard package as shown in the table below. To use this package one has to include the following clause:. Types defined in the Package Standard of the std Library. Not supported by the Foundation synthesis program. User-defined Types. One can introduce new types by using the type declaration, which names the type and specifies its value range. The syntax is. A subtype is a subset of a previously defined type. The last example above illustrates the use of subtypes.

Another example of a subtype is,. Note that floating point data types are not supported by the Xilinx Foundation synthesis program. The physical type definition includes a units identifier as follows,.

Here are some object declarations that use the above types,. Notice that a space must be left before the unit name. The physical data types are not supported by the Xilinx Foundation Express synthesis program. In order to use our own types, we need either to include the type definition inside an architecture body or to declare the type in a package. Enumerated Types. An enumerated type consists of lists of character literals or identifiers.

The enumerated type can be very handy when writing models at an abstract level. The syntax for an enumerated type is,. If one does not initialize the signal, the default initialization is the leftmost element of the list. Enumerated types have to be defined in the architecture body or inside a package as shown in the section above. In order to use this type one has to include the clause before each entity declaration.

It is possible that multiple drivers are driving a signal. In that case there could be a conflict and the output signal would be undetermined. In order to resolve the value of the output, one can call up a resolution function. These are usually a user-written function that will resolve the signal. One can then use the following declaration for signal OUT1. Composite Types: Array and Record. Composite data objects consist of a collection of related data elements in the form of an array or record.

Before we can use such objects one has to declare the composite type first. Thus this array looks as follows:. We can now declare objects of these data types. Some examples are given. To access individual elements of an array we specify the index. Multidimensional arrays can be declared as well by using a similar syntax as above,. To access an element one specifies the index, e. Sometimes it is more convenient not to specify the dimension of the array when the array type is declared.

This is called an unconstrained array type. The syntax for the array declaration is,. The range is now specified when one declares the array object,. A second composite type is the records type.

A record consists of multiple elements that may be of different types. The syntax for a record type is the following:. SIZE : integer range 0 to ;. To access values or assign values to records, one can use one of the following methods:. Type Conversions. Since VHDL is a strongly typed language one cannot assign a value of one data type to a signal of a different data type.

Sometimes one cannot avoid using different types. To allow assigning data between objects of different types, one needs to convert one type to the other. An example follows. The syntax of a type conversion is as follows:. Here are the conditions that must be fulfilled for the conversion to be possible. VHDL supports 5 types of attributes. Predefined attributes are always applied to a prefix such as a signal name, variable name or a type. Attributes are used to return various types of information about a signal, variable or type.

This expression checks for the arrival of a positive clock edge. To find out how much time has passed since the last clock edge, one can use the following attribute:. Several attributes of a scalar type, scalar-type, are supported. The following table shows some of these attributes. By using array attributes one can return an index value corresponding to the array range. The number N between parentheses refers to the dimension.

For a one-dimensional array, one can omit the number N as shown in the examples below. Lets assume the following arrays, declared as follows:. VHDL supports different classes of operators that operate on signals, variables and constants. The different classes of operators are summarized below. Logical operators. Relational operators. Shift operators. Addition operators. Unary operators. Multiplying op. Miscellaneous op.

The order of precedence is the highest for the operators of class 7, followed by class 6 with the lowest precedence for class 1. Unless parentheses are used, the operators with the highest precedence are applied first. Operators of the same class have the same precedence and are applied from left to right in an expression. The expression.

The xor is executed on a bit-per-bit basis. Logic operators. They are used to define Boolean logic expression or to perform bit-per-bit operations on arrays of bits. They give a result of the same type as the operand Bit or Boolean. These operators can be applied to signals, variables and constants. Notice that the nand and nor operators are not associative. One should use parentheses in a sequence of nand or nor operators to prevent a syntax error:.

Some examples of relational operations are:. For discrete array types, the comparison is done on an element-per-element basis, starting from the left towards the right, as illustrated by the last two examples. Shift left logical fill right vacated bits with the 0. Left: Any one-dimensional array type with elements of type bit or Boolean; Right: integer.

Same as left type. Shift right logical fill left vacated bits with 0. Shift left arithmetic fill right vacated bits with rightmost bit. Shift right arithmetic fill left vacated bits with leftmost bit. Rotate left circular. Rotate right circular. The operand is on the left of the operator and the number integer of shifts is on the right side of the operator.

As an example,. NUM1 srl 2;. When a negative integer is given, the opposite action occurs, i. As an example. The addition operators are used to perform arithmetic operation addition and subtraction on operands of any numeric type. In order to use these operators one has to specify the ieee. Numeric type. Same as left operand. Same type. Array or element type. Same array type. An example of concatenation is the grouping of signals into a single bus [4].

Multiplying operators. The multiplying operators are used to perform mathematical functions on numeric types integer or floating point. Any integer or floating point. Any physical type. Integer or real type. Same as left. Any integer or real type. Same as right. Any integer or real t ype. Any integer type. The multiplication operator is also defined when one of the operands is a physical type and the other an integer or real type.

The remainder rem and modulus mod are defined as follows:. The result of the rem operator has the sign of its first operand while the result of the mod operators has the sign of the second operand. Some examples of these operators are given below. Miscellaneous operators. These are the absolute value and exponentation operators that can be applied to numeric types. The logical negation not results in the inverse polarity but the same type.

Left Operand Type. Right Operand Type. Result Type. Integer type. Floating point. Absolute value. Any numeric type. Logical negation. Any bit or Boolean type. As discussed earlier, VHDL provides means to represent digital circuits at different levels of representation of abstraction, such as the behavioral and structural modeling.

In this section we will discuss different constructs for describing the behavior of components and circuits in terms of sequential statements. The basis for sequential modeling is the process construct. As you will see, the process construct allows us to model complex digital systems, in particular sequential circuits. A process statement is the main construct in behavioral modeling that allows you to use sequential statements to describe the behavior of a system over time.

The syntax for a process statement is. An example of a positive edge-triggered D flip-flop with asynchronous clear input follows. A process is declared within an architecture and is a concurrent statement. However, the statements inside a process are executed sequentially. Like other concurrent statements, a process reads and writes signals and values of the interface input and output ports to communicate with the rest of the architecture.

One can thus make assignments to signals that are defined externally e. The sensitivity list is a set of signals to which the process is sensitive.

Any change in the value of the signals in the sensitivity list will cause immediate execution of the process. If the sensitivity list is not specified, one has to include a wait statement to make sure that the process will halt.

Notice that one cannot include both a sensitivity list and a wait statement. The keyword begin signals the start of the computational part of the process. The statements are sequentially executed, similarly as a conventional software program. As a result, changes made to variables will be available immediately to all subsequent statements within the same process. For an example that illustrates the difference between signal and variable assignments see the section on Data Types difference between signals and variables.

The previous example of the D flip-flop illustrates how to describe a sequential circuit with the process statement. Although the process is mainly used to describe sequential circuits, one can also describe combinational circuits with the process construct. The following example illustrates this for a Full Adder, composed of two Half Adders. This example also illustrates how one process can generate signals that will trigger other processes when events on the signals in its sensitivity list occur [3].

For the Full Adder:. Figure 5 illustrates how the Full Adder has been modeled. P1: process A, B. P2: process int1, int2, Cin. Of course, one could simplify the behavioral model significantly by using a single process. The if statement executes a sequence of statements whose sequence depends on one or more conditions.

The syntax is as follows:. Each condition is a Boolean expression. Nesting of if statements is allowed. An example of an if statement was given earlier for a D Flip-flop with asynchronous clear input. The if statement can be used to describe combinational circuits as well. The following example illustrates this for a 4-to-1 multiplexer with inputs A, B, C and D, and select signals S0 and S1.

This statement must be inside a process construct. A slightly different way of modeling the same multiplexer is shown below,. If statements are often used to implement state diagrams. For an example of a Mealy machine see Example Mealy Machine later on.

Case statements. The case statement executes one of several sequences of statements, based on the value of a single expression. The syntax is as follows,. The case statement evaluates the expression and compares the value to each of the choices. The when clause corresponding to the matching choice will have its statements executed. The following rules must be adhered to:. An example of a case statement using an enumerated type follows. A, B, C, D: out bit ;. This is a useful operator to indicate ranges that are not adjacent e.

Another example using the case construct is a 4-to-1 MUX. Since the case statement is a sequential statement, one can have nested case statements. Loop statements. A loop statement is used to repeatedly execute a sequence of sequential statements. The syntax for a loop is as follows:. Labels are optional but are useful when writing nested loops. The next and exit statement are sequential statements that can only be used inside a loop.

This loop has no iteration scheme. It will be executed continuously until it encounters an exit or next statement. The basic loop as well as the while-loop must have at least one wait statement. As an example, lets consider a 5-bit counter that counts from 0 to When it reaches 31, it will start over from 0. Example of a basic loop to implement a counter that counts from 0 to COUNT: out integer ;.

The while … loop evaluates a Boolean iteration condition. When the condition is TRUE, the loop repeats, otherwise the loop is skipped and the execution will halt. The syntax for the while…loop is as follows,. The condition of the loop is tested before each iteration, including the first iteration. If it is false, the loop is terminated. The for-loop uses an integer iteration scheme that determines the number of iterations.

Next and Exit Statement. The next statement skips execution to the next iteration of a loop statement and proceeds with the next iteration. The when keyword is optional and will execute the next statement when its condition evaluates to the Boolean value TRUE. The exit statement skips the rest of the statements, terminating the loop entirely, and continues with the next statement after the exited loop.

Notice that the difference between the next and exit statement, is that the exit statement terminates the loop. Wait statement. The wait statement will halt a process until an event occurs.

There are several forms of the wait statement,. The Xilinx Foundation Express has implemented only the first form of the wait statement. For the first example the process will wait until a positive-going clock edge occurs, while for the second example, the process will wait until a negative-going clock edge arrives. The last two examples are equivalent to the first one positive-edge or transitions.

The hardware implementation for these three statements will be identical. It should be noted that a process that contains a wait statement can not have a sensitivity list.

If a process uses one or more wait statements, the Foundation Express synthesizer will use sequential logic. The results of the computations are stored in flip-flops. Null statement. The null statement states that no action will occur. It can be useful in a case statement where all choices must be covered, even if some of them can be ignored.

As an example, consider a control signal CNTL in the range 0 to Example of a Mealy Machine. The sequence following detector recognizes the input bit sequence X: "". The machine will keep checking for the proper bit sequence and does not reset to the initial state after it recognizes the string. In case we are implementing a Mealy machine, the output is associated with the transitions as indicated on the following state diagram Figure 6.

Figure 6: Sequence detector , realized as a Mealy Machine. The VHDL file is given below. Behavioral modeling can be done with sequential statements using the process construct or with concurrent statements. The first method was described in the previous section and is useful to describe complex digital systems. In this section, we will use concurrent statements to describe behavior. This method is usually called dataflow modeling.

The dataflow modeling describes a circuit in terms of its function and the flow of data through the circuit. This is different from the structural modeling that describes a circuit in terms of the interconnection of components. Concurrent signal assignments are event triggered and executed as soon as an event on one of the signals occurs.

In the remainder of the section we will describe several concurrent constructs for use in dataflow modeling.

Simple Concurrent signal assignments. We have discussed several concurrent examples earlier in the tutorial. In this section we will review the different types of concurrent signal assignments. A simple concurrent signal assignment is given in the following examples,.

As soon as an event occurs on one of the signals, the expression will be evaluated. Another example is given below of a 4-bit adder circuit. Notice that we specified the package: IEEE. Conditional Signal assignments. The syntax for the conditional signal assignment is as follows:.

If no condition is found to be TRUE, the target signal will receive the value of the final expression. If more than one condition is true, the value of the first condition that is TRUE will be assigned. An example of a 4-to-1 multiplexer using conditional signal assignments is shown below. The conditional signal assignment will be re-evaluated as soon as any of the signals in the conditions or expression change. The when-else construct is useful to express logic function in the form of a truth table.

An example of the same multiplexer as above is given below in a more compact form. Notice that this construct is simpler than the If-then-else construct using the process statement or the case statement. An alternative way to define the multiplexer is the case construct inside a process statement, as discussed earlier. Selected Signal assignments. The selected signal assignment is similar to the conditional one described above.

The expression selected is the first with a matching choice. The choice can be a static expression e. The following rules must be followed for the choices:. An example of a 4-to-1 multiplexer is given below. The equivalent process statement would make use of the case construct. Similarly to the when-else construct, the selected signal assignment is useful to express a function as a truth table, as illustrated above.

The choices can express a single value, a range or combined choices as shown below. In the above example, all eight choices are covered and only once. The others choice must the last one used. As an example, lets consider a full adder with inputs A, B and C and outputs sum and cout,. Notice : In the example above we had to define an internal vector INS A,B,C of the input signals to use as part of the with-select-when statement.

A structural way of modeling describes a circuit in terms of components and its interconnection. Each component is supposed to be defined earlier e. At the lowest hierarchy each component is described as a behavioral model, using the basic logic operators defined in VHDL. In general structural modeling is very good to describe complex digital systems, though a set of components in a hierarchical fashion. A structural description can best be compared to a schematic block diagram that can be described by the components and the interconnections.

VHDL provides a formal way to do this by. The components and signals are declared within the architecture body,. Component declaration. Before components can be instantiated they need to be declared in the architecture declaration section or in the package declaration. The component declaration consists of the component name and the interface ports. The component name refers to either the name of an entity defined in a library or an entity explicitly defined in the VHDL file see example of the four bit adder.

The list of interface ports gives the name, mode and type of each port, similarly as is done in the entity declaration. A few examples of component declaration follow:. DATA: inout integer range 0 to ;.

As mentioned earlier, the component declaration has to be done either in the architecture body or in the package declaration.

If the component is declared in a package, one does not have to declare it again in the architecture body as long as one uses the library and use clause. Component Instantiation and interconnections. The component instantiation statement references a component that can be. The syntax for the components instantiation is as follows,. The instance name or label can be any legal identifier and is the name of this particular instance.

The component name is the name of the component declared earlier using the component declaration statement. The port name is the name of the port and signal is the name of the signal to which the specific port is connected. The above port map associates the ports to the signals through named association.